FPGA Based Hardware Co-Simulation of an Area and Power Efficient FIR Filter for Wireless Communication Systems

DOI
10.15415/jtmge.2010.11008

AUTHORS

Rajesh Kumar, Swapna Devi and S.S. Pattnaik

ABSTRACT

“In this paper FPGA based hardware co-simulation of an area and power efficient FIR filter for wireless communication systems is presented. The implementation is based on distributed arithmetic (DA) which substitutes multiply-and-accumulate operations with look up table (LUT) accesses. Parallel Distributed arithmetic (PDA) look up table approach is used to implement an FIR Filter taking optimal advantage of the look up table structure of FPGA using VHDL. The proposed design is hardware co-simulated using System Generator10.1, synthesized with Xilinx ISE 10.1 software, and implemented on Virtex-4 based xc4vlx25-10ff668 target device. Results show that the proposed design operates at 17.5 MHz throughput and consumes 0.468W power with considerable reduction in required resources to implement the design as compared to Coregen and add/shift based design styles. Due to this reduction in required resources the proposed design can also be implemented on Spartan-3 FPGA device to provide cost effective solution for DSP and wireless communication applications.”

KEYWORDS

FPGA, PDA, Simulation Add/Shift, VHDL.

REFERENCES

  • D.J. Allred, H. Yoo, V. Krishnan, W. Huang, and D. Anderson, “A Novel High Performance Distributed Arithmetic Adaptive Filter Implementation on an FPGA”, in Proc. IEEE Int.Conference on Acoustics,Speech, and Signal Processing (ICASSP’04), Vol. 5, pp. 161-164, 2004
  • K.N. Macpherson and R.W. Stewart “Area efficient FIR filters for high speed FPGA Implementation”, IEE Proc.-Vis. Image Signal Process., Vol. 153, No. 6, Page711-720, December 2006.
  • Patrick Longa and Ali Miri “Area-Efficient FIR Filter Design on FPGAs using Distributed Arithmetic”, pp248-252 IEEE International Symposium on Signal Processing and Information Technology,2006.
  • S. A. White, “Applications of distributed arithmetic to digital signal processing: A tutorial review,” IEEE ASSP Magazine, vol. 6, pp. 4–19, July 1989.
  • Matthew Ownby and Dr. Wagdy H. Mahmoud “A Design methodology for implementing DSP with Xilinx System Generator for Matlab”, Page 404-408 IEEE 2002.
  • Shahnam Mirzaei, Anup Hosangadi, Ryan Kastner “FPGA Implementation of High Speed FIR Filters Using Add and Shift Method”, pp 308-313 in IEEE International conference on Computer Design, ICCD, 2006.
  • Heejong Yoo and David V. Anderson “Hardware-Efficient Distributed Arithmetic Architecture for High-Order Digital Filters”, ppV125-128 in Proc. IEEE , ICASSP 2005.

RNI Registration No. CHAENG/2016/68678